Selected research and engineering projects spanning FPGA, EDA, security, AI, and embedded systems
Integration of the Yosys front-end synthesizer with the Odin-II partial technology mapper inside the Verilog-to-Routing (VTR) open-source FPGA CAD flow. The joint synthesizer improves device resource utilization by enabling coarse-grained netlists and hard/soft logic trade-off decisions with architecture awareness. Accepted at FCCM '22 and FPGA '22, now part of VTR mainline.
A heuristic partial mapping plugin for the Odin-II synthesis tool within VTR, leveraging a genetic algorithm (GA) to explore mapping decisions and optimize logic block footprint on target FPGA architectures. Implemented in C/C++ as a pluggable optimizer, enabling architecture-aware synthesis without full re-synthesis. Published at RSP '20.
A hardware/software co-design project on the Altera DE0-Nano-SoC FPGA board (Xilinx Zynq-7000 also evaluated), using Evolvable Hardware (EHW) techniques—Variable-length Radio Circuit (VRC) combined with Cartesian Genetic Programming (CGP)—to offload computationally intensive image processing filters (edge detection, blurring) onto custom evolved hardware accelerators. Recognized as the best project by Iran's largest ISP, SHATEL.
An embedded system measuring blood pressure and heart rate using an ATMEGA32 microprocessor. The device integrates a pressure sensor, ADC module, and hardware timer to capture oscillometric waveforms and compute systolic/diastolic values. Includes an LCD display interface and UART serial output. A foundational computational biology project from undergraduate studies at the University of Tehran.
A Python-based facial recognition system using deep metric learning, the dlib library, and HOG (Histogram of Oriented Gradients) feature extraction. Implements a face detection and embedding pipeline that encodes faces as high-dimensional vectors and matches identities using distance metrics. Supports real-time recognition from webcam streams.
A fully functional digital oscilloscope implemented on the Altera DE0-Nano FPGA board, comprising four independent hardware subsystems: horizontal time-base control, trigger detection circuit, vertical amplitude scaling, and waveform display driver. Implemented in Verilog, the design demonstrates core digital signal acquisition principles on reconfigurable hardware.
A cryptographic security interface for the open-source Ceph distributed storage system. Implements symmetric encryption modes—AES-CBC, AES-CTR, and AES-GCM—to provide transparent data-at-rest protection for high-performance storage clusters. Designed for HPC and cloud environments where security must not compromise throughput.