Seyed Alireza Damghani

FPGA / EDA Software Engineer

4+ years building production-grade EDA tools at Intel and Altera — spanning synthesis compilers, logic optimization, device modeling, HW/SW co-design, and agentic AI-powered developer toolchains. Published researcher in top FPGA venues (FPGA, FCCM, FPL, TCAD).

About Me Publications Contact
8 Publications
4+ Yrs Exp.
7 Projects
github.com/sdamghan LinkedIn Profile Google Scholar sd@mghan.xyz

Recent News

Paper "Efficient Security Interface for High-performance Ceph Storage Systems" published in Future Generation Computer Systems (2025). DOI →
Joined Altera as FPGA Software Engineer (Jan 2025) — working on device modeling, configuration pipelines, and agentic AI toolchains.
"Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research" published in IEEE TCAD (2023). DOI →
Joined Intel Canada as FPGA Software Engineer (Sep 2022) — contributing to Quartus compiler: synthesis, timing analysis, logic optimization, and formal verification.
Yosys+Odin-II partial technology mapper accepted as poster at FCCM '22, New York. All news →

Explore

👤
About
Biography & work history
 📄
Publications
8 papers — FPGA, FCCM, FPL, TCAD
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Notable Projects
EDA, FPGA, AI & embedded systems
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Contact
GitHub, LinkedIn, Scholar, Email