Career milestones, publications, and announcements
"Efficient Security Interface for High-performance Ceph Storage Systems" by F. Khoda Parast, S.A. Damghani, B. Kelly, Y. Wang, and K.B. Kent. Read →
Working on device modeling, HW/SW codesign, configuration pipelines, register mapping, and agentic AI toolchains.
"Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research" published in IEEE TCAD. Read →
Contributing to the Quartus Compiler: synthesis, elaboration, timing analysis, logic optimization, formal verification, and CI/CD testing.
"Odin-II Partial Technology Mapping for Yosys Coarse-grained Netlists in VTR" accepted at IEEE FCCM 2022, New York. DOI →
"Machine Learning-Based Hard/Soft Logic Trade-offs in VTR" published at IEEE RSP 2022, Shanghai. DOI →
"Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR" accepted at FPGA '22. DOI →
Led development and integration of Yosys+Odin-II synthesis compiler into the VTR open-source EDA tool mainstream.
Successfully defended Master of Computer Science thesis at the University of New Brunswick.
"Heterogeneous Logic Implementation for Adders in VTR" published at IEEE RSP 2021. DOI →
"Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research" published at FPL 2021. arXiv →
Offered a research assistant position at the University of New Brunswick, contributing to the VTR CAD flow and Odin-II development.
Appointed official Odin-II maintainer in the Verilog-to-Routing CAD flow — responsible for code reviews, issue resolution, and new features.
"Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin-II" published at IEEE RSP 2020. DOI →
Summer internship at Tech Impact as Data Analyst / Business Strategy Intern.